Status Register
| BUSY | Module Busy: Asserted when module is currently busy handling a transaction to an external flash device |
| IP_ACC | IP Access: Asserted when transaction currently executed was initiated by IP bus. |
| AHB_ACC | AHB Access: Asserted when the transaction currently executed was initiated by AHB bus. |
| AHBGNT | AHB Command priority Granted: Asserted when another module has been granted priority of AHB Commands against IP Commands |
| AHBTRN | AHB Access Transaction pending: Asserted when there is a pending request on the AHB interface |
| AHB0NE | AHB 0 Buffer Not Empty: Asserted when AHB 0 buffer contains data. |
| AHB1NE | AHB 1 Buffer Not Empty: Asserted when AHB 1 buffer contains data. |
| AHB2NE | AHB 2 Buffer Not Empty: Asserted when AHB 2 buffer contains data. |
| AHB3NE | AHB 3 Buffer Not Empty: Asserted when AHB 3 buffer contains data. |
| AHB0FUL | AHB 0 Buffer Full: Asserted when AHB 0 buffer is full. |
| AHB1FUL | AHB 1 Buffer Full: Asserted when AHB 1 buffer is full. |
| AHB2FUL | AHB 2 Buffer Full: Asserted when AHB 2 buffer is full. |
| AHB3FUL | AHB 3 Buffer Full: Asserted when AHB 3 buffer is full. |
| RXWE | RX Buffer Watermark Exceeded: Asserted when the number of valid entries in the RX Buffer exceeds the number given in the QSPI_RBCT[WMRK] field |
| RXFULL | RX Buffer Full: Asserted when the RX Buffer is full, i |
| RXDMA | RX Buffer DMA: Asserted when RX Buffer read out via DMA is active i.e DMA is requested or running. |
| TXEDA | Tx Buffer Enough Data Available |
| TXWA | TX Buffer watermark Available |
| TXDMA | TXDMA |
| TXFULL | TX Buffer Full: Asserted when no more data can be stored. |
| DLPSMP | Data learning pattern sampling point: The sampling point found by the controller with the data learning pattern |